To test complex devices, test engineers must rely on the vector sets generated by verification engineers. Unfortunately, verification engineers—who work in a software simulation environment—often have ...

Philippe Luc, director of verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF ...

Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, chief executive officer for VTool; Adnan Hamid, chief ...

BENGALURU, India — Two engineers at Oski Technology Inc. (Fremont, Calif.) have demonstrated a formal verification planning process and associated verification strategy that they say is a ...

Emulation allows the register transfer level (RTL) source code to be used as the model but with enough processing performance to enable system-level work, especially when it involves software ...

To a savvy chip design verification engineer, VIP is much more than a catchy acronym. Designers understand that verification intellectual property is a mainstay of the verification flow with libraries ...

Behavioral modeling has caught on quite fast in the analog verification community. A RTL like description on analog, RF and mixed-signal blocks has opened up more possibilities of thorough top-level ...

Tell us a little about your professional and/or educational background. I did my bachelors’ degree in electrical and electronics in India. After graduating, I worked at Intel for a year as a design ...

Aparna Mohan pioneered a groundbreaking verification methodology for security-critical semiconductor designs that has transformed how the industry approaches security verification, yielding ...

Today’s semiconductor workforce is already 43% smaller than it was in 2000, even as demand for chips has grown exponentially.