DATAQUEST

Huawei presents Tau (τ) scaling law, enabling breakthroughs in transistor density and system performance

Innovative technologies such as LogicFolding, can be used to continuously compress signal propagation delay and steadily ...
MSN on MSN

A chip the size of rice can pack tens of billions of transistors

Engineers at MIT have produced the smallest three-dimensional transistor ever reported, a device so compact that a chip ...
EDN

Taking power analysis to the transistor level for a full chip

Almost every chip being taped out today is mixed-signal in nature. In addition to increased integration of analog and RF blocks, designers are using complex power-management techniques to minimize ...
EDN

Synopsys Rolls Out Transistor-Level Static Timing Analysis

To address emerging custom circuit design challenges, Mountain View, Calif.-based EDA giant Synopsys Inc. today unveiled its anticipated next-generation transistor-level static timing analysis tool, ...

HUAWEI Presents the Tau Scaling Law, Enabling Breakthroughs in Transistor Density and System Performance

On Monday, at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai, He Tingbo, President of HUAWEI's Semiconductor Business Department, presented the Tau (τ) Scaling Law, ...